The present invention relates to computer architectures and, in particular, to a method and apparatus for managing virtual memory in a computer system in order to reduce memory access latency.
During the execution of the computer program, a computer processor may access a memory to read data needed as the arguments for executing instructions or to write data produced by the execution of those instructions. The accessed data may be identified by a unique physical address of a memory location holding that data.
Modern computer systems may hide the physical addresses of data accessed by a program by mapping those physical addresses to a virtual address space. Typically, using virtual addressing, processes (programs in execution) running on these computer systems, may see a linear virtual address space unique to each process. Virtual addressing provides a number of advantages including simplifying programming (by providing a uniform and simple address space), prevention of interference between concurrently executing processes (by segregating the address spaces of different processes), and providing illusion of larger than available physical address space size to the processes (by automatically moving physical memory and disk or storage).
In operation, a virtual memory system providing virtual addressing in a computer processor may employ a “page table” that translates between virtual addresses and physical addresses. In one embodiment, a virtual address may be expressed as a page address and an offset address. Offset address being a location within a given page relative to its page address. The page table maps a virtual page address to a physical page address using a table-like structure. The content of the page table (for example, linked pairs of virtual page addresses and physical page addresses) may be cached, for example, in a hardware cache structure termed a “translation lookaside buffer” (TLB), that holds a portion of the page table content that has been recently used to be rapidly accessible. The process of translation between virtual addresses and physical addresses may first look at the TLB and only if the necessary information is not found in the TLB, move to examine the page table. In the later case when necessary information is unavailable in TLB, significant delay is possible.
Thus, the indirection of accessing memory by looking up the TLB and/or the page table can significantly delay the speed of memory access.